In many applications, including digital communications, clock and data recovery (CDR) systems are employed to recover correct timing (i.e., frequency and phase) of an input data stream. This timing information is then employed to sample the input data stream to receiver the user data for decoding. A serializer/deserializer (SERDES) device is commonly used in high speed communications to convert data between serial and parallel interfaces in each transmit/receive direction.
SERDES devices often employ an encoding scheme that supports DC-balance, provides framing, and guarantees signal transitions. Guaranteed transitions allow a receiver to extract the embedded clock signal, while control codes allow framing, typically on the start of a data packet. This encoding scheme also improves error detection with running disparity, providing separation of data bits from control bits, and permits derivation of byte and word synchronization.
Future generations of the SERDES are likely to move to digital signal processing (DSP)-based architectures which perform more data path signal processing than conventional analog SERDES devices. In both digital and analog types of SERDES, there is usually a variable gain amplifier (VGA) followed by an analog equalizer (AEQ). The VGA and AEQ together form an analog front end (AFE) which provides for gain control as well as some level of analog equalization/higher frequency peaking or group delay compensation. A conventional analog SERDES communication channel is shown in FIG. 1 of U.S. patent application Ser. No. 13/288,096, filed Nov. 3, 2011, incorporated by reference herein in its entirety.
In contrast to an analog SERDES implementation such as that described in the above-referenced patent application, in a DSP-based architecture, the AFE is followed by an analog to digital converter (ADC) which produces quantized or digital samples at a symbol or baud rate. These finite precision samples are subsequently processed further for equalization using a digital feed-forward equalizer (FFE) or digital decision feedback equalizer (DIGDFE). The DIGDFE equalized signal may be followed by a final digital slicing operation to provide the final decisions. For non-return to zero (NRZ) transmitted data modulation, the data slicing produces binary symbol decisions 1, −1 (or 1, 0 in unipolar notation). For pulse amplitude 4 level (PAM4) modulation the data slicing produces 4 level symbol decisions 3, 1, −1, −3. Depending on the DIGDFE, the final decisions may be produced inherently as part of the DIGDFE equalization process and an additional data slicer may not be needed.
In addition to equalization, the SERDES performs clock/data recovery (CDR) to recover phase and frequency offsets and determine where symbol or baud spaced samples should be taken. In an analog SERDES, for example, a bang-bang phase detector (BBPD) is followed by a digital loop filter and a clock generation element to determine what phase the recovered clock should sample the analog signal at the output of the AFE. The clock generation element could be an analog phase interpolator (API), a phase selection circuit (PSC) or a phase mixer (PM), or a voltage controlled oscillator (VCO). The BBPD includes various slicers or latches which quantize the sampled analog signal and use these slicer outputs to compute a timing gradient estimate which drives the digital loop filter. Note that the BBPD for the analog SERDES requires two separate physical clocks, a data clock and a transition clock, which is phase offset by 0.5 T or half a symbol period from a main data clock.
CDR needs to be performed for the DSP-based SERDES as well in this case the recovered clock determines the sampling phase for the ADC. The ADC output samples can be used to drive a digital phase detector (PD). In the DSP-based SERDES, there generally is no transition clock, only a data clock.
There is a tradeoff between CDR latency and optimal sampling. An DSP implementing equalization functions incurs delay or latency. This means that the later in the equalization chain the data/error signals are obtained from, the more latency is incurred in providing these signals to the CDR phase detector, thus degrading the dynamic performance behavior of the CDR. The system robustness might be degraded accordingly in terms of bit error rate or jitter tolerance performance.
On the other hand, the last equalization stage is used to obtain the final data decisions. If these decisions or any other signals obtained from the last equalization stage are used to create the phase detector input, the recovered clock sampling phase determined by the CDR might provide higher quality or more robust final decisions. Thus, there is a tradeoff between the CDR dynamic performance behavior with better dynamic performance obtained with smaller latency signals derived earlier in the equalization chain verses the improvement of CDR sampling phase (or its mean/average value) quality or accuracy by using higher latency signals derived later in the equalization chain. Both the dynamic CDR performance and sample phase mean affect the bit error rate robustness of the SERDES system.